Bit vs. symbol interleaving for parallel concatenated trellis coded modulation

This paper compares bit v.s. symbol interleaving for parallel-concatenated trellis-coded turbo codes, employing the turbo encoder structure proposed in [1]. To compare systems optimized with the same techniques, the paper extends the turboencoder design procedure proposed in [2] to bitinterleaved systems. We discuss a method to jointly design the multiple required interleavers for the bitinterleaved system, and a procedure to select constituent encoders that can take advantage of the interleaver structure to achieve a low error floor. Simulation results for the designed bit-interleaved system show better performance than bit-interleaved performance reported in the literature. The symbolinterleaved system though achieves an earlier convergence, especially with an increased number of decoder iterations, but at the cost of a slightly higher error floor.